1. Field of the Invention
The present invention relates to a memory device, and more particularly to the fabrication of a memory cell of a flash memory.
2. Description of the Prior Art
Complementary metal-oxide-semiconductor (CMOS) memory can be divided into two main categories: random access memory (RAM) and read-only memory (ROM). ROM""s market share has been continuously growing in the past few years, and further growth in the near future is foreseen, especially for flash memory in which a single cell is electrically programmable and a block, sector or page of cells that are electrically erasable at the same time. Due to the flexibility of flash memory against electrically programmable read-only memory (EPROM), electrically programmable but erasable via ultraviolet exposure, the market share of flash memory is also experiencing rapid growth. Electrically erasable and programmable read-only memory (EEPROM), electrically erasable and programmable per single byte, will be manufactured for specific applications only, since they use more area and are more expensive. In recent years, flash memory has found interesting applications in electrical consumer products such as: digital cameras, digital video cameras, cellular phones, laptop computers, mobile MP3 players, and Personal Digital Assistants (PDA""s). Since portability of these electrical consumer products is strongly prioritized by consumers, the products"" size must be minimal. As a result, the capacity of the flash memory must be enlarged, and functions have to be maximized while size is reduced. The capacity of flash memory has increased from 4 to 256 MB, and will increase to even 1 GB in the near future. With the increase in packing density for flash memory, floating gates and control gates have to be made as small as possible. In conventional processes, masks are usually used to define the gates in flash memory. FIGS. 1A to 1G show the manufacturing processes of a conventional flash memory device.
As shown in FIG. 1A, a semiconductor substrate 100 is provided. An LOCOS oxidation process is performed to form a field insulating layer (not shown) on the substrate 100. The field insulating layer isolates each active area. A first insulating layer 110 is formed on the substrate 100 within the active area. The first insulating layer 110 can be oxide formed by oxidation and has a thickness of from 50 to 200 angstroms. Then, a first conductive layer 115, which has a thickness of about 100 to 2000 angstroms, is formed on the first insulating layer 110. The first conductive layer 115 is usually doped polycrystalline silicon formed by chemical vapor deposition (CVD) process. Then, a first masking layer 120, with a thickness of about 500 to 2000 angstroms, is formed on the first conductive layer 115 by depositing a silicon nitride layer.
As shown in FIG. 1B, the first masking layer 120 is removed by performing an etching process to define the first opening 125 and to expose the surface of the first conductive layer 115. The remaining first masking layer 120 will be referred to as 120xe2x80x2 hereafter. An oxidation is performed on the exposed surface of the first conductive layer 115 and a first insulating layer 130 is formed.
As shown in FIG. 1C, the remaining first masking layer 120xe2x80x2 is removed by performing an etching process. Then, using the first insulating layer 130 as a hard mask, a portion of the first conductive layer 115 and the first insulating layer 110 are sequentially removed to expose the surface of the substrate 100 by anisotropic etching. The portions of the first conductive layer 115 and the first insulating layer 110 under the floating gate insulating layer 130 remain. The remaining first conductive layer 115 forms a floating gate 136. The remaining first insulating layer 110 will be expressed as a first gate insulating layer 132.
As shown in FIG. 1D, a second insulating layer 134 is formed on the surface of the substrate 100, the oxide layer 130, the floating gate 136 and the first gate insulating layer 132. The second insulating layer 132, which has a thickness of about 50 to 250 angstroms, is an oxide and is formed by CVD.
As shown in FIG. 1E, a second conductive layer 135 is formed on the second insulating layer 134. The second conductive layer 135 is usually made of the doped polycrystalline silicon formed by CVD.
As shown in FIG. 1F, portions of the second conductive layer 135 and the second insulating layer 134 are removed by photolithography and etching to form a second opening 142 and a third opening 144. The remaining second conductive layer 135 forms the control gate 170. The remaining second insulating layer 134 will be expressed as a second gate insulating layer 136. Next, a source region 146 is formed on the exposed substrate 100 by implanting N-type ions, such as phosphorus or arsenic into the substrate 100, which is exposed in the second opening 142.
As shown in FIG. 1G, an oxide layer (not shown) is formed to cover the surface and the sidewalls of the control gate 170, the second opening 142 and the third opening 144. Etching is performed to remove portions of the oxide layer and form the sidewall spacers 150 on the sidewalls of the second opening 142 and the third opening 144. A drain region 160 is formed on the exposed substrate 100 by implanting N-type ions, such as phosphorus or arsenic into the substrate 100, which is exposed in the third opening 144. The manufacture of a cell of flash memory is thus completed.
As shown in FIG. 1H, applying the above processes, the second opening 142 and the third opening 144 may shift when photolithography is misaligned. Thus, the lengths of the bottom portion (gate length; L1 and L2) of the control gates are different, and L1 is longer than L2 in this figure. Current leakage may occur if the gate length is short, and current minimization may occur if the gate length is long, such that the performance of a flash memory cell does not match the design. Thus, the lengths of the control gates in the flash memory cell must be equal to ensure the functions and characteristics of the flash memory.
Due to the rapid advancement of the integration of memory, size of all elements must continuously decrease to achieve high integration. Conventional fabrication of flash memory relies upon masks to define sizes and positions of elements, but limitation of mask alignment causes problems for finer line width, where alignments are difficult. Even tiny misalignments may cause function fail in semiconductor elements.
In order to overcome the above problems, the invention forms sidewall spacers on the sidewalls of xe2x80x9cZ typexe2x80x9d and xe2x80x9creversed Z typexe2x80x9d control gates. This results in easy control for the process and sizes of the control gates and avoid the influence of line width. Length at the bottom of the control gate is consequently assured, which improves the conventional fabrication of flash memory. By having the sidewall spacers, disagreement among lengths of control gates caused by misalignment when forming control gates and contact window is avoided, thus characteristics of flash memory are improved. The method provided in this invention is not only useful in fabricating highly integrated flash memory, but defects caused by misalignment in conventional process are avoided.
This invention provides a method for fabricating a flash memory cell, comprising the following steps: providing a semiconductor substrate; defining an active area on the substrate; forming a first gate insulating layer within the active area; forming a first conductive layer on the first gate insulating layer; forming a first masking layer on the first conductive layer; removing a portion of the first masking to form a first opening and expose the first conductive layer; forming a floating gate insulating layer on the exposed surface of the first conductive layer by an oxidation process; removing a portion of the first masking between the two adjacent floating gate insulating layers to expose the surface of the first conductive layer; removing a portion of the first conductive layer and the first insulating layer between the two adjacent floating gate insulating layers using the floating gate insulating layer as a hard mask, such that a second opening is formed to expose the surface of the substrate; forming a source region by implanting impurity ions through the second opening into the substrate; forming a second insulating layer on the surface of the floating gate insulating layer and the first masking layer and filling the second opening; performing a planarization process using the first masking layer as a stop layer to remove a portion of the second insulating layer on the first masking layer and leave the portion on the floating gate insulating layer and in the second opening; removing the first masking layer; forming a floating gate region using the remaining second insulating layer as a mask and etching portions of the first conductive layer and the first insulating layer to expose the surface of the substrate, such that the first conductive layer remaining under the floating gate insulating layer becomes a floating gate, the remaining first insulating layer becomes a gate insulating layer, and then, the remaining second insulating layer, the gate insulating layer and the floating gate are combined as the floating gate region; forming a third insulating layer to cover the surface of the substrate and the surface and the sidewalls of the floating gate region; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; removing portions of the fourth insulating layer, such that the fourth insulating layer remaining on the sidewalls of the second conductive layer forms first sidewall spacers; forming control gates and a tunneling oxide using the first sidewall spacers as a hard mask and removing portions of the second conductive layer and the third insulating layer to form a third opening on the remaining second insulating layer and a fourth opening on the substrate, such that the remaining second conductive layer becomes the control gates, and then the remaining third insulating layer becomes a tunneling oxide; forming second sidewall spacers on the sidewalls of the third opening and the fourth opening; and forming a drain region on the substrate within the fourth opening.